drivers/gpu/drm/amd/amdgpu/cik_sdma.c

181

return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

195

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

464

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

480

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

205

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

221

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

439

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

455

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

369

wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

396

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

716

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1104

WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

683

wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

726

WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

357

wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

399

ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

719

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

724

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

761

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

197

wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

235

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

248

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

568

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

573

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

609

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

80

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),