mmSCRATCH_REG0
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
tmp = RREG32(mmSCRATCH_REG0);
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
tmp = RREG32(mmSCRATCH_REG0);
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
tmp = RREG32(mmSCRATCH_REG0);
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
tmp = RREG32(mmSCRATCH_REG0);
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
tmp = RREG32(mmSCRATCH_REG0);
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);