drivers/gpu/drm/amd/amdgpu/cik.c

1004

WREG32(mmD1VGA_CONTROL, d1vga_control);

drivers/gpu/drm/amd/amdgpu/cik.c

978

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/cik.c

988

WREG32(mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1805

mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1849

mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1752

mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

526

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

791

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

962

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1070

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1260

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/si.c

1276

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/si.c

1286

WREG32(mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/si.c

1302

WREG32(mmD1VGA_CONTROL, d1vga_control);

drivers/gpu/drm/amd/amdgpu/vi.c

600

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/vi.c

610

WREG32(mmD1VGA_CONTROL,

drivers/gpu/drm/amd/amdgpu/vi.c

626

WREG32(mmD1VGA_CONTROL, d1vga_control);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1810

addr = mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

399

offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

402

offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

405

offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

408

offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

411

offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

417

value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

425

dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);