CLK_UART4
[CLK_UART4] = &uart4_clk.common.hw,
[CLK_UART4] = &clk_uart4.common.hw,
[CLK_UART4] = &uart4_clk.common.hw,
CLK_UART4, "uart4",
CLK_UART4, "uart4",
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
[CLK_UART4] = &clk_uart4.common.hw,
[CLK_UART4] = &clk_uart4.common.hw,
[CLK_UART4] = &uart4_clk.common.hw,
[CLK_UART4] = &uart4_clk.common.hw,