CLK_UART3
[CLK_UART3] = &uart3_clk.common.hw,
[CLK_UART3] = &clk_uart3.common.hw,
[CLK_UART3] = &uart3_clk.common.hw,
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
[CLK_UART3] = &clk_uart3.common.hw,
[CLK_UART3] = &clk_uart3.common.hw,
[CLK_UART3] = &uart3_clk.common.hw,
[CLK_UART3] = &uart3_clk.common.hw,