CLK_UART1
[CLK_UART1] = &uart1_clk.common.hw,
[CLK_UART1] = &clk_uart1.common.hw,
[CLK_UART1] = &uart1_clk.common.hw,
GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
[CLK_UART1] = &clk_uart1.common.hw,
[CLK_UART1] = &clk_uart1.common.hw,
[CLK_UART1] = &uart1_clk.common.hw,
[CLK_UART1] = &uart1_clk.common.hw,