CLK_UART0
[CLK_UART0] = &uart0_clk.common.hw,
[CLK_UART0] = &clk_uart0.common.hw,
[CLK_UART0] = &uart0_clk.common.hw,
GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
[CLK_UART0] = &clk_uart0.common.hw,
[CLK_UART0] = &clk_uart0.common.hw,
[CLK_UART0] = &uart0_clk.common.hw,
[CLK_UART0] = &uart0_clk.common.hw,
[CLK_UART0] = &uart0_clk.common.hw,