mmMP0_SMN_C2PMSG_101
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,