drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h

82

#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

325

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

327

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

330

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

339

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

347

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

350

WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

374

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

395

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

405

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);