mmIH_VMID_0_LUT
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;