drivers/clk/mediatek/clk-mt2701.c

504

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,

drivers/clk/mediatek/clk-mt2712.c

656

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),

drivers/clk/mediatek/clk-mt6735-topckgen.c

343

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 1, 7, 0, 0),

drivers/clk/mediatek/clk-mt6765.c

402

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,

drivers/clk/mediatek/clk-mt6795-topckgen.c

466

TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),

drivers/clk/mediatek/clk-mt7622.c

406

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,

drivers/clk/mediatek/clk-mt7629.c

480

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,

drivers/clk/mediatek/clk-mt7981-topckgen.c

301

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,

drivers/clk/mediatek/clk-mt7986-topckgen.c

184

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,

drivers/clk/mediatek/clk-mt7988-topckgen.c

127

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,

drivers/clk/mediatek/clk-mt8135.c

375

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),

drivers/clk/mediatek/clk-mt8173-topckgen.c

545

MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),

drivers/clk/mediatek/clk-mt8192.c

598

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",

drivers/clk/mediatek/clk-mt8365.c

429

MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,