mmDMA2_QM_GLBL_CFG1
WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
mask |= 1U << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2);