mmDMA0_QM_PQ_PI_0
WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
mask |= 1U << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2);