mmDMA0_QM_GLBL_CFG1
WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0);
WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT);
cfg1 = RREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset);
WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset,
WREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset, cfg1);
mask |= 1U << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2);