mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE
block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
(mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
#define RTR_MSTR_IF_OFFSET (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)