CLK_TOP_MEM_SEL
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,
MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,