drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1299

address = CRTC_REG(mmCRTC_GSL_CONTROL);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1368

address = CRTC_REG(mmCRTC_GSL_CONTROL);

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

45

.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

48

.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

51

.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

54

.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

57

.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

60

.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

106

.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

109

.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

112

.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

115

.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

44

.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

47

.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

50

.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

53

.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

56

.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

59

.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),