CLK_TOP_IRTX_SEL
MUX_GATE_CLR_SET_UPD(CLK_TOP_IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 1, 31, 0, 0),
MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,