drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

512

u32 mixercfg[5] = { 0 };

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

527

mixercfg[0] = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

552

mixercfg[0] |= mix << cfg->shift;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

553

mixercfg[1] |= ext << cfg->ext_shift;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

555

mixercfg[cfg->idx] |= mix_ext << cfg->shift;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

561

DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg[0]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

562

DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

563

DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

564

DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

566

DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

159

mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,