mii_rw
if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
if (mii_rw(dev, np->phyaddr,
reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
phy_reserved = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
if (mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr,
reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_control_1000 = mii_rw(dev, np->phyaddr,
if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR,
mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
mii_rw(dev, np->phyaddr, MII_BMCR,
mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);