mgb4_write_reg
mgb4_write_reg(video, regs->config, 0x1 | (config & ~0x3));
mgb4_write_reg(&voutdev->mgbdev->cmt, addr[i], reg_set[i]);
mgb4_write_reg(video, regs->config, config & ~0x1);
mgb4_write_reg(video, regs->config, 0x1 | (config & ~0x3));
mgb4_write_reg(&vindev->mgbdev->cmt, addr[i], reg_set[i]);
mgb4_write_reg(video, regs->config, config & ~0x1);
mgb4_write_reg(&mgbdev->video, 0xD4, mgbdev->module_version);
mgb4_write_reg(regs, reg, val);
mgb4_write_reg(&mgbdev->video, voutdev->config->regs.config,
mgb4_write_reg(&mgbdev->video, voutdev->config->regs.config,
mgb4_write_reg(&voutdev->mgbdev->video,
mgb4_write_reg(&st->mgbdev->video, 0xB4, 1U << 11);
mgb4_write_reg(&st->mgbdev->video, 0xA0, scan.data);
mgb4_write_reg(video, voutdev->config->regs.padding,
mgb4_write_reg(video, vindev->config->regs.padding, 0);
mgb4_write_reg(video, vindev->config->regs.padding, vindev->padding);
mgb4_write_reg(video, vindev->config->regs.config, config);
mgb4_write_reg(video, vindev->config->regs.timer, timer);
mgb4_write_reg(video, 0xB4, 1U << vindev->config->vin_irq);
mgb4_write_reg(video, 0xB4, 1U << vindev->config->err_irq);
mgb4_write_reg(video, regs->config, 0x00000001);
mgb4_write_reg(video, regs->sync, 0x03E80002);
mgb4_write_reg(video, regs->padding, 0x00000000);
mgb4_write_reg(video, regs->config, dp << 9);
mgb4_write_reg(&mgbdev->video, voutdev->config->regs.padding, 0);
mgb4_write_reg(video, config->regs.padding, voutdev->padding);
mgb4_write_reg(video, voutdev->config->regs.config, config);
mgb4_write_reg(video, voutdev->config->regs.timer, timer);
mgb4_write_reg(video, 0xB4, 1U << voutdev->config->irq);
mgb4_write_reg(video, regs->config, 0x00000001);
mgb4_write_reg(video, regs->resolution, (1280 << 16) | 640);
mgb4_write_reg(video, regs->hsync, 0x00283232);
mgb4_write_reg(video, regs->vsync, 0x40141F1E);
mgb4_write_reg(video, regs->frame_limit, MGB4_HW_FREQ / 60);
mgb4_write_reg(video, regs->padding, 0x00000000);
mgb4_write_reg(video, regs->config, source | dp << 4);