Symbol: CLK_TOP_AUDINTBUS_SEL
drivers/clk/mediatek/clk-mt2701.c
520
MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
drivers/clk/mediatek/clk-mt6735-topckgen.c
352
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, 0, 0),