Symbol: CLK_TOP_APLL2_DIV1
drivers/clk/mediatek/clk-mt6795-topckgen.c
519
DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
drivers/clk/mediatek/clk-mt8173-topckgen.c
614
DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),