Symbol: CLK_TOP_APLL2_DIV0
drivers/clk/mediatek/clk-mt6795-topckgen.c
518
DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
drivers/clk/mediatek/clk-mt8173-topckgen.c
613
DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),