Symbol: CLK_TOP_APLL1_DIV2
drivers/clk/mediatek/clk-mt6795-topckgen.c
513
DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
drivers/clk/mediatek/clk-mt8173-topckgen.c
608
DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),