Symbol: CLK_TOP_APLL1_DIV1
drivers/clk/mediatek/clk-mt6795-topckgen.c
512
DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
drivers/clk/mediatek/clk-mt8173-topckgen.c
607
DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),