CLK_TOP_APLL12_DIV4
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
.div_clk_id = CLK_TOP_APLL12_DIV4,
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
.div_clk_id = CLK_TOP_APLL12_DIV4,
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
.div_clk_id = CLK_TOP_APLL12_DIV4,
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",