CLK_TOP_APLL12_DIV0
GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
.div_clk_id = CLK_TOP_APLL12_DIV0,
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
.div_clk_id = CLK_TOP_APLL12_DIV0,
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
.div_clk_id = CLK_TOP_APLL12_DIV0,
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",