CLK_TIMER1
GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0,
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
COMPOSITE_NODIV(CLK_TIMER1, "clk_timer1", clk_timer1_parents_p, 0,
[CLK_TIMER1] = &clk_timer1.common.hw,
[CLK_TIMER1] = &clk_timer1.common.hw,
static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x208, 0, 0);