CLK_TIMER0
GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0,
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
COMPOSITE_NODIV(CLK_TIMER0, "clk_timer0", clk_timer0_parents_p, 0,
[CLK_TIMER0] = &clk_timer0.common.hw,
[CLK_TIMER0] = &clk_timer0.common.hw,
static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x208, 1, 0);