drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

1040

struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

1043

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h

122

struct mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h

133

struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

105

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

109

mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

110

clk_disable_unprepare(mdp5_kms->vsync_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

13

static struct mdp5_kms *get_kms(struct drm_encoder *encoder)

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

23

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

30

if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

42

vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

61

mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

62

mdp5_write(mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

65

mdp5_write(mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

67

mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

68

mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

69

mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id),

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

72

mdp5_write(mdp5_kms, REG_MDP5_PP_AUTOREFRESH_CONFIG(pp_id), 0x0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

79

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

84

ret = clk_set_rate(mdp5_kms->vsync_clk,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

85

clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE));

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

91

ret = clk_prepare_enable(mdp5_kms->vsync_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

98

mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1038

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1067

pm_runtime_get_sync(&mdp5_kms->pdev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1075

pm_runtime_put_sync(&mdp5_kms->pdev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1086

struct mdp5_kms *mdp5_kms = get_kms(state->crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1097

if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1268

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1271

mdp_irq_update(&mdp5_kms->base);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

169

struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

170

struct msm_kms *kms = &mdp5_kms->base.base;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

216

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

330

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

332

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

334

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

337

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

339

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

341

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

346

val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

347

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

350

val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

351

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

365

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

385

mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

390

val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

392

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

397

mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

402

val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

404

mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

492

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

493

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

505

mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

507

mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

512

spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

515

spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

538

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

539

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

573

mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

576

mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

699

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

71

static struct mdp5_kms *get_kms(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

743

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

884

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

924

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

925

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

927

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

930

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

933

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

936

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

939

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

944

mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

955

struct mdp5_kms *mdp5_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

956

struct platform_device *pdev = mdp5_kms->pdev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

957

struct msm_kms *kms = &mdp5_kms->base.base;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

120

mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

121

spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

159

struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

164

set_display_intf(mdp5_kms, intf);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

64

struct mdp5_kms *get_kms(struct mdp5_ctl_manager *ctl_mgr)

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

74

struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

77

mdp5_write(mdp5_kms, reg, data);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

83

struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

86

return mdp5_read(mdp5_kms, reg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

89

static void set_display_intf(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

95

spin_lock_irqsave(&mdp5_kms->resource_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

96

intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

101

mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

102

mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

103

mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

104

mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

105

mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

106

mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

107

mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

110

mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

111

mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

112

mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

113

mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

123

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

13

static struct mdp5_kms *get_kms(struct drm_encoder *encoder)

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

137

mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

149

mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf));

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

157

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

168

mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

24

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

251

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

254

return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf));

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

260

struct mdp5_kms *mdp5_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

263

return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf));

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

93

mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

96

mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

97

mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

98

mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

103

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

104

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

116

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

117

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

25

struct mdp5_kms *mdp5_kms = container_of(irq, struct mdp5_kms, error_handler);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

32

struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

33

drm_state_dump(mdp5_kms->dev, &p);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

39

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

40

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

43

mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

44

mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

51

struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

52

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

53

struct mdp_irq *error_handler = &mdp5_kms->error_handler;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

70

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

71

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

74

mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

81

struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

82

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

86

enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

87

status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

88

mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

122

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

130

mdp5_state->mdp5_kms = mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

140

if (mdp5_state->mdp5_kms->smp)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

141

mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

153

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

154

pm_runtime_get_sync(&mdp5_kms->pdev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

159

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

160

pm_runtime_put_sync(&mdp5_kms->pdev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

165

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

168

global_state = mdp5_get_existing_global_state(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

170

if (mdp5_kms->smp)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

171

mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

181

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

184

for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

190

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

193

global_state = mdp5_get_existing_global_state(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

195

if (mdp5_kms->smp)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

196

mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

199

static void mdp5_destroy(struct mdp5_kms *mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

203

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

212

mdp_kms_destroy(&mdp5_kms->base);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

213

mdp5_destroy(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

236

static int mdp5_disable(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

24

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

240

mdp5_kms->enable_count--;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

241

WARN_ON(mdp5_kms->enable_count < 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

243

clk_disable_unprepare(mdp5_kms->tbu_rt_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

244

clk_disable_unprepare(mdp5_kms->tbu_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

245

clk_disable_unprepare(mdp5_kms->ahb_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

246

clk_disable_unprepare(mdp5_kms->axi_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

247

clk_disable_unprepare(mdp5_kms->core_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

248

clk_disable_unprepare(mdp5_kms->lut_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

25

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

253

static int mdp5_enable(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

257

mdp5_kms->enable_count++;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

259

clk_prepare_enable(mdp5_kms->ahb_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

260

clk_prepare_enable(mdp5_kms->axi_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

261

clk_prepare_enable(mdp5_kms->core_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

262

clk_prepare_enable(mdp5_kms->lut_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

263

clk_prepare_enable(mdp5_kms->tbu_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

264

clk_prepare_enable(mdp5_kms->tbu_rt_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

269

static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

273

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

303

static int modeset_init_intf(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

306

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

308

struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

327

encoder = construct_encoder(mdp5_kms, intf, ctl);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

338

mdp5_cfg_get_hw_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

357

encoder = construct_encoder(mdp5_kms, intf, ctl);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

379

static int modeset_init(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

381

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

393

for (i = 0; i < mdp5_kms->num_intfs; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

394

ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

408

num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

415

for (i = 0; i < mdp5_kms->num_hwpipes; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

416

struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

464

static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

467

struct device *dev = &mdp5_kms->pdev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

471

version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

503

struct mdp5_kms *mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

513

mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

515

pdev = mdp5_kms->pdev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

517

ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

523

config = mdp5_cfg_get_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

534

mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

536

mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

54

spin_lock_irqsave(&mdp5_kms->resource_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

540

vm = msm_kms_init_vm(mdp5_kms->dev, pdev->dev.parent);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

55

mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

550

ret = modeset_init(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

56

spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

572

static void mdp5_destroy(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

574

if (mdp5_kms->rpm_enabled)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

575

pm_runtime_disable(&mdp5_kms->pdev->dev);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

577

drm_atomic_private_obj_fini(&mdp5_kms->glob_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

58

mdp5_ctlm_hw_reset(mdp5_kms->ctlm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

580

static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

584

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

597

hwpipe->idx = mdp5_kms->num_hwpipes;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

598

mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

604

static int hwpipe_init(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

621

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

624

ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

630

ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

636

ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

642

ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

651

static int hwmixer_init(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

653

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

657

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

670

mixer->idx = mdp5_kms->num_hwmixers;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

671

mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

677

static int interface_init(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

679

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

684

hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

702

intf->idx = mdp5_kms->num_intfs;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

703

mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

712

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

717

mdp5_kms->dev = dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

719

drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

726

clk_set_rate(mdp5_kms->core_clk, 200000000);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

729

mdp5_kms->rpm_enabled = true;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

73

mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

731

read_mdp_hw_revision(mdp5_kms, &major, &minor);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

733

mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

734

if (IS_ERR(mdp5_kms->cfg)) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

735

ret = PTR_ERR(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

736

mdp5_kms->cfg = NULL;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

740

config = mdp5_cfg_get_config(mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

741

mdp5_kms->caps = config->hw->mdp.caps;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

744

clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

75

return to_mdp5_global_state(mdp5_kms->glob_state.state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

751

if (mdp5_kms->caps & MDP_CAP_SMP) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

752

mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

753

if (IS_ERR(mdp5_kms->smp)) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

754

ret = PTR_ERR(mdp5_kms->smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

755

mdp5_kms->smp = NULL;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

760

mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

761

if (IS_ERR(mdp5_kms->ctlm)) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

762

ret = PTR_ERR(mdp5_kms->ctlm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

763

mdp5_kms->ctlm = NULL;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

767

ret = hwpipe_init(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

771

ret = hwmixer_init(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

775

ret = interface_init(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

781

mdp5_destroy(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

817

struct mdp5_kms *mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

825

mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

826

if (!mdp5_kms)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

833

mdp5_kms->pdev = pdev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

835

spin_lock_init(&mdp5_kms->resource_lock);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

837

mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys");

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

838

if (IS_ERR(mdp5_kms->mmio))

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

839

return PTR_ERR(mdp5_kms->mmio);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

842

ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

845

ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

848

ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

85

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

851

ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

856

get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

857

get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

858

get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

864

mdp5_kms->base.base.irq = irq;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

866

return msm_drv_probe(&pdev->dev, mdp5_kms_init, &mdp5_kms->base.base);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

879

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

88

priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

883

return mdp5_disable(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

890

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

894

return mdp5_enable(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

171

static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

173

WARN_ON(mdp5_kms->enable_count <= 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

174

writel(data, mdp5_kms->mmio + reg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

177

static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

179

WARN_ON(mdp5_kms->enable_count <= 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

180

return readl(mdp5_kms->mmio + reg);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

271

int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

272

void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

71

#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

81

struct mdp5_kms *mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

88

struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

19

static int get_right_pair_idx(struct mdp5_kms *mdp5_kms, int lm)

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

28

for (i = 0; i < mdp5_kms->num_hwmixers; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

29

struct mdp5_hw_mixer *mixer = mdp5_kms->hwmixers[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

43

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

53

for (i = 0; i < mdp5_kms->num_hwmixers; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

54

struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

74

pair_idx = get_right_pair_idx(mdp5_kms, cur->lm);

drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c

81

*r_mixer = mdp5_kms->hwmixers[pair_idx];

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

101

ret = mdp5_smp_assign(mdp5_kms->smp, &new_global_state->smp,

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

125

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

144

if (mdp5_kms->smp) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

146

mdp5_smp_release(mdp5_kms->smp, &state->smp, hwpipe->pipe);

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

15

struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

25

old_global_state = mdp5_get_existing_global_state(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

30

for (i = 0; i < mdp5_kms->num_hwpipes; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

31

struct mdp5_hw_pipe *cur = mdp5_kms->hwpipes[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

64

for (j = i + 1; j < mdp5_kms->num_hwpipes;

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

67

mdp5_kms->hwpipes[j];

drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c

94

if (mdp5_kms->smp) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

218

struct mdp5_kms *mdp5_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

256

if (mdp5_kms->smp) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

260

blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

27

static struct mdp5_kms *get_kms(struct drm_plane *plane)

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

461

static void set_scanout_locked(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

465

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

469

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

473

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

475

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

477

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

479

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

484

static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

486

uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

489

mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

493

static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

507

mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

510

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

513

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

516

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

519

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

522

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

529

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

533

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

537

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

540

mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

575

struct mdp5_kms *mdp5_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

576

struct device *dev = mdp5_kms->dev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

598

struct mdp5_kms *mdp5_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

599

struct device *dev = mdp5_kms->dev->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

669

static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

68

struct mdp5_kms *mdp5_kms = get_kms(state->plane);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

709

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

710

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

711

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

72

if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

741

static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

759

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

763

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

767

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

771

mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

775

mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

779

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

792

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

798

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

805

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

808

mdp5_write_pixel_ext(mdp5_kms, pipe, format,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

813

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

815

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

817

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

819

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

821

mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

824

mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

830

csc_enable(mdp5_kms, pipe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

833

csc_disable(mdp5_kms, pipe);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

836

set_scanout_locked(mdp5_kms, pipe, fb);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

845

struct mdp5_kms *mdp5_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

936

mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

942

mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

161

struct mdp5_kms *mdp5_kms = get_kms(smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

162

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

251

struct mdp5_kms *mdp5_kms = get_kms(smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

257

mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

259

mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i),

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

266

struct mdp5_kms *mdp5_kms = get_kms(smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

269

for (i = 0; i < mdp5_kms->num_hwpipes; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

270

struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

273

mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

275

mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

277

mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe),

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

32

struct mdp5_kms *get_kms(struct mdp5_smp *smp)

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

325

struct mdp5_kms *mdp5_kms = get_kms(smp);

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

337

for (i = 0; i < mdp5_kms->num_hwpipes; i++) {

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

338

struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

360

struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_block *cfg)

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

362

struct drm_device *dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

371

smp->dev = mdp5_kms->dev;

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

375

global_state = mdp5_get_existing_global_state(mdp5_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h

60

struct mdp5_kms;

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h

69

struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,