drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

119

struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

120

struct msm_kms *kms = &mdp4_kms->base.base;

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

143

static void setup_mixer(struct mdp4_kms *mdp4_kms)

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

145

struct drm_mode_config *config = &mdp4_kms->dev->mode_config;

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

164

mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

170

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

175

mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

176

mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

177

mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

178

mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

202

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

203

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

204

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

205

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

206

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

207

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

208

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

209

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

212

setup_mixer(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

218

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

231

mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

236

mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

237

mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

238

mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

242

mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

243

mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

246

mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

248

mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

251

mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

252

mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

253

mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

261

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

272

mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

273

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

277

spin_lock_irqsave(&mdp4_kms->dev->event_lock, flags);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

280

spin_unlock_irqrestore(&mdp4_kms->dev->event_lock, flags);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

290

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

297

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

302

mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

357

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

358

struct msm_kms *kms = &mdp4_kms->base.base;

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

374

mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

377

mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

378

mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

383

mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

384

mdp4_kms->blank_cursor_iova);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

395

mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

407

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

408

struct msm_kms *kms = &mdp4_kms->base.base;

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

529

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

538

!(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

559

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

561

mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

568

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

571

intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

602

mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

62

static struct mdp4_kms *get_kms(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

79

struct mdp4_kms *mdp4_kms = get_kms(crtc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c

94

mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

101

mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

109

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

125

mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

23

static struct mdp4_kms *get_kms(struct drm_encoder *encoder)

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

33

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

59

mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

62

mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

63

mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

64

mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

67

mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

68

mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

70

mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

71

mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

74

mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

77

mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

78

mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

79

mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

80

mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

86

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c

91

mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

104

mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

116

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

145

mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

22

static struct mdp4_kms *get_kms(struct drm_encoder *encoder)

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

33

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

63

mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

66

mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

67

mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

68

mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

71

mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

72

mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

73

mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

74

mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

77

mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

78

mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

79

mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

82

mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

83

mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

89

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c

94

mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

104

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

106

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

109

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

23

struct mdp4_kms *mdp4_kms = container_of(irq, struct mdp4_kms, error_handler);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

30

struct drm_printer p = drm_info_printer(mdp4_kms->dev->dev);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

31

drm_state_dump(mdp4_kms->dev, &p);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

37

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

38

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

39

mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

40

mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

41

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

47

struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

48

struct mdp_irq *error_handler = &mdp4_kms->error_handler;

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

61

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

62

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

63

mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

64

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

70

struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

71

struct drm_device *dev = mdp4_kms->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

75

enable = mdp4_read(mdp4_kms, REG_MDP4_INTR_ENABLE);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

76

status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS) & enable;

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

77

mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

92

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

94

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

97

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

123

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

124

struct device *dev = mdp4_kms->dev->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

126

if (mdp4_kms->blank_cursor_iova)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

127

msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->vm);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

128

drm_gem_object_put(mdp4_kms->blank_cursor_bo);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

137

if (mdp4_kms->rpm_enabled)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

140

mdp_kms_destroy(&mdp4_kms->base);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

163

int mdp4_disable(struct mdp4_kms *mdp4_kms)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

167

clk_disable_unprepare(mdp4_kms->clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

168

clk_disable_unprepare(mdp4_kms->pclk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

169

clk_disable_unprepare(mdp4_kms->lut_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

170

clk_disable_unprepare(mdp4_kms->axi_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

175

int mdp4_enable(struct mdp4_kms *mdp4_kms)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

179

clk_prepare_enable(mdp4_kms->clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

180

clk_prepare_enable(mdp4_kms->pclk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

181

clk_prepare_enable(mdp4_kms->lut_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

182

clk_prepare_enable(mdp4_kms->axi_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

188

static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

191

struct drm_device *dev = mdp4_kms->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

20

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

21

struct drm_device *dev = mdp4_kms->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

27

if (mdp4_kms->rev > 1) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

28

mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

29

mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

290

static int modeset_init(struct mdp4_kms *mdp4_kms)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

292

struct drm_device *dev = mdp4_kms->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

32

mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

35

mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

355

ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

369

static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

37

clk = clk_get_rate(mdp4_kms->clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

372

struct drm_device *dev = mdp4_kms->dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

375

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

376

version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

377

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

388

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

39

if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

398

ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

406

mdp4_kms->dev = dev;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

408

if (mdp4_kms->vdd) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

409

ret = regulator_enable(mdp4_kms->vdd);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

416

clk_set_rate(mdp4_kms->clk, max_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

418

read_mdp_hw_revision(mdp4_kms, &major, &minor);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

427

mdp4_kms->rev = minor;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

429

if (mdp4_kms->rev >= 2) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

430

if (!mdp4_kms->lut_clk) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

435

clk_set_rate(mdp4_kms->lut_clk, max_clk);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

439

mdp4_kms->rpm_enabled = true;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

445

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

446

mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

447

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

448

mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

449

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

452

vm = msm_kms_init_vm(mdp4_kms->dev, NULL);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

460

ret = modeset_init(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

466

mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

467

if (IS_ERR(mdp4_kms->blank_cursor_bo)) {

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

468

ret = PTR_ERR(mdp4_kms->blank_cursor_bo);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

470

mdp4_kms->blank_cursor_bo = NULL;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

474

ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->vm,

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

475

&mdp4_kms->blank_cursor_iova);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

49

mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

50

mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

503

struct mdp4_kms *mdp4_kms;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

506

mdp4_kms = devm_kzalloc(dev, sizeof(*mdp4_kms), GFP_KERNEL);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

507

if (!mdp4_kms)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

510

mdp4_kms->mmio = msm_ioremap(pdev, NULL);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

511

if (IS_ERR(mdp4_kms->mmio))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

512

return PTR_ERR(mdp4_kms->mmio);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

518

mdp4_kms->base.base.irq = irq;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

52

mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

524

mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

525

if (IS_ERR(mdp4_kms->vdd))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

526

mdp4_kms->vdd = NULL;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

528

mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

529

if (IS_ERR(mdp4_kms->clk))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

53

mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

530

return dev_err_probe(dev, PTR_ERR(mdp4_kms->clk), "failed to get core_clk\n");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

532

mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

533

if (IS_ERR(mdp4_kms->pclk))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

534

mdp4_kms->pclk = NULL;

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

536

mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

537

if (IS_ERR(mdp4_kms->axi_clk))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

538

return dev_err_probe(dev, PTR_ERR(mdp4_kms->axi_clk), "failed to get axi_clk\n");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

54

mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

544

mdp4_kms->lut_clk = devm_clk_get_optional(&pdev->dev, "lut_clk");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

545

if (IS_ERR(mdp4_kms->lut_clk))

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

546

return dev_err_probe(dev, PTR_ERR(mdp4_kms->lut_clk), "failed to get lut_clk\n");

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

548

return msm_drv_probe(&pdev->dev, mdp4_kms_init, &mdp4_kms->base.base);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

55

mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

57

if (mdp4_kms->rev >= 2)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

58

mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

59

mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

62

mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

63

mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

64

mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

65

mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

66

mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

67

mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

69

if (mdp4_kms->rev > 1)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

70

mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

79

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

80

mdp4_enable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

85

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

86

mdp4_disable(mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

96

struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

99

for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

149

int mdp4_disable(struct mdp4_kms *mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

150

int mdp4_enable(struct mdp4_kms *mdp4_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

43

#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

45

static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

47

writel(data, mdp4_kms->mmio + reg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

50

static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

52

return readl(mdp4_kms->mmio + reg);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

121

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

126

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

130

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

135

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

139

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

144

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

190

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

191

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

192

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG2, 0x30);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

197

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

206

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

236

mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

239

mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_PERIOD, vsync_period);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

240

mdp4_write(mdp4_kms, REG_MDP4_LCDC_VSYNC_LEN, vsync_len);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

241

mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

244

mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VSTART, display_v_start);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

245

mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

246

mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

247

mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR,

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

250

mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_SKEW, lcdc_hsync_skew);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

251

mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

252

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL,

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

255

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VSTART, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

256

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_VEND, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

26

static struct mdp4_kms *get_kms(struct drm_encoder *encoder)

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

263

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

268

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

278

mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

294

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

331

mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

49

struct mdp4_kms *mdp4_kms = get_kms(encoder);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

67

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

72

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

76

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

81

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

85

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

90

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

94

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c

99

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3),

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

19

static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll)

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

60

struct mdp4_kms *mdp4_kms = get_kms(lvds_pll);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

69

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

72

mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

74

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

77

while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED))

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

86

struct mdp4_kms *mdp4_kms = get_kms(lvds_pll);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

90

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c

91

mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

138

struct mdp4_kms *mdp4_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

141

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

145

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

149

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

151

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

153

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

155

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

159

static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

165

mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

170

mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

173

mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

178

mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

181

mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_LV(pipe, i),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

197

struct mdp4_kms *mdp4_kms = get_kms(plane);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

277

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

281

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

285

mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

289

mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

295

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

309

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

320

mdp4_write_csc_config(mdp4_kms, pipe, csc);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

323

mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

324

mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

325

mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

328

mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),

drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c

50

static struct mdp4_kms *get_kms(struct drm_plane *plane)