CLK_SPI1
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &clk_spi1.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
COMPOSITE(CLK_SPI1, "clk_spi1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0,
COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
K210_FUNC(CLK_SPI1, OUT),