CLK_SPI0
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &clk_spi0.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
COMPOSITE(CLK_SPI0, "clk_spi0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0,
COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,