mci_readl
reg = mci_readl(host, UHS_REG_EXT);
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
clksel = mci_readl(host, CLKSEL64);
clksel = mci_readl(host, CLKSEL);
clksel = mci_readl(host, CLKSEL64);
clksel = mci_readl(host, CLKSEL);
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
clksel = mci_readl(host, CLKSEL64);
clksel = mci_readl(host, CLKSEL);
clksel = mci_readl(host, CLKSEL64);
clksel = mci_readl(host, CLKSEL);
clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
drto_clks = mci_readl(host, TMOUT) >> 8;
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
val = mci_readl(host, UHS_REG);
val = mci_readl(host, ENABLE_SHIFT);
val = mci_readl(host, DDR_REG);
regval = mci_readl(host, TUNING_CTRL);
val = mci_readl(host, ENABLE_SHIFT);
val = mci_readl(host, DDR_REG);
raw_value = mci_readl(host, TIMING_CON1);
raw_value = mci_readl(host, TIMING_CON0);
u32 reg_value = mci_readl(host, UHS_REG_EXT);
temp = mci_readl(host, CTRL);
temp = mci_readl(host, INTMASK);
temp = mci_readl(host, INTMASK);
temp = mci_readl(host, CTRL);
clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
regs = mci_readl(host, UHS_REG);
regs = mci_readl(host, PWREN);
regs = mci_readl(host, PWREN);
status = mci_readl(host, STATUS);
uhs = mci_readl(host, UHS_REG);
seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
mci_readl(host, WRTPRT) & BIT(0) ? 1 : 0;
seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
reset = mci_readl(host, RST_N);
clk_en_a_old = mci_readl(host, CLKENA);
int_mask = mci_readl(host, INTMASK);
if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
cmd->resp[3] = mci_readl(host, RESP0);
cmd->resp[2] = mci_readl(host, RESP1);
cmd->resp[1] = mci_readl(host, RESP2);
cmd->resp[0] = mci_readl(host, RESP3);
cmd->resp[0] = mci_readl(host, RESP0);
ctrl = mci_readl(host, CTRL);
drto_clks = mci_readl(host, TMOUT) >> 8;
drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
status = mci_readl(host, MINTSTS);
(dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
SDMMC_GET_FCNT(mci_readl(host, STATUS)))
status = mci_readl(host, MINTSTS);
pending = mci_readl(host, MINTSTS); /* read-only mask reg */
pending = mci_readl(host, IDSTS64);
clk_en_a = mci_readl(host, CLKENA);
pending = mci_readl(host, IDSTS);
host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
pending = mci_readl(host, MINTSTS); /* read-only mask reg */
pending = mci_readl(host, MINTSTS); /* read-only mask reg */
temp = mci_readl(host, INTMASK);
i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
fifo_size = mci_readl(host, FIFOTH);
host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
cto_clks = mci_readl(host, TMOUT) & 0xff;
cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
u32 bmod = mci_readl(host, BMOD);
temp = mci_readl(host, CTRL);
temp = mci_readl(host, BMOD);
temp = mci_readl(host, CTRL);
temp = mci_readl(host, BMOD);
fifoth_val = mci_readl(host, FIFOTH);
return !(mci_readl(host, CDETECT) & BIT(0));