mci_writel
mci_writel(host, UHS_REG_EXT, reg);
mci_writel(host, MPSBEGIN0, 0);
mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
mci_writel(host, CLKSEL64, clksel);
mci_writel(host, CLKSEL, clksel);
mci_writel(host, CLKSEL64, clksel);
mci_writel(host, CLKSEL, clksel);
mci_writel(host, HS400_DQS_EN, dqs);
mci_writel(host, HS400_DLINE_CTRL, strobe);
mci_writel(host, CLKSEL64, clksel);
mci_writel(host, CLKSEL, clksel);
mci_writel(host, CLKSEL64, clksel);
mci_writel(host, CLKSEL, clksel);
mci_writel(host, TMOUT, ~0);
mci_writel(host, TMOUT, tmout);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, UHS_REG, val);
mci_writel(host, ENABLE_SHIFT, val);
mci_writel(host, DDR_REG, val);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, ENABLE_SHIFT, val);
mci_writel(host, DDR_REG, val);
mci_writel(host, GPIO, 0x0);
mci_writel(host, UHS_REG_EXT, reg_value);
mci_writel(host, ENABLE_SHIFT, enable_shift);
mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
mci_writel(host, TMOUT, ~0);
mci_writel(host, TIMING_CON1,
mci_writel(host, TIMING_CON0,
mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
mci_writel(host, UHS_REG_EXT, reg_value);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, RINTSTS, ALL_INT_CLR);
mci_writel(host, CTRL, temp);
mci_writel(host, INTMASK, temp);
mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
mci_writel(host, INTMASK, temp);
mci_writel(host, CTRL, temp);
mci_writel(host, FIFOTH, host->fifoth_val);
mci_writel(host, CLKENA, 0);
mci_writel(host, CLKENA, 0);
mci_writel(host, CLKSRC, 0);
mci_writel(host, CLKDIV, div);
mci_writel(host, CLKENA, clk_en_a);
mci_writel(host, CTYPE, host->ctype);
mci_writel(host, TMOUT, tmout);
mci_writel(host, BYTCNT, data->blksz*data->blocks);
mci_writel(host, BLKSIZ, data->blksz);
mci_writel(host, UHS_REG, regs);
mci_writel(host, PWREN, regs);
mci_writel(host, PWREN, regs);
mci_writel(host, UHS_REG, uhs);
mci_writel(host, RST_N, reset);
mci_writel(host, RST_N, reset);
mci_writel(host, CLKENA, clk_en_a);
mci_writel(host, INTMASK, int_mask);
mci_writel(host, RINTSTS, 0xFFFFFFFF);
mci_writel(host, CTRL, ctrl);
mci_writel(host, CMDARG, arg);
mci_writel(host, CMD, SDMMC_CMD_START | cmd);
mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
mci_writel(host, RINTSTS, SDMMC_INT_CD);
mci_writel(host, RINTSTS,
mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
mci_writel(host, CLKENA, clk_en_a);
mci_writel(host, INTMASK, temp);
mci_writel(host, RINTSTS, 0xFFFFFFFF);
mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
mci_writel(host, TMOUT, 0xFFFFFFFF);
mci_writel(host, FIFOTH, host->fifoth_val);
mci_writel(host, CLKENA, 0);
mci_writel(host, CLKSRC, 0);
mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
mci_writel(host, RINTSTS, 0xFFFFFFFF);
mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
mci_writel(host, CLKENA, 0);
mci_writel(host, CLKSRC, 0);
mci_writel(host, FIFOTH, host->fifoth_val);
mci_writel(host, TMOUT, 0xFFFFFFFF);
mci_writel(host, RINTSTS, 0xFFFFFFFF);
mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
mci_writel(host, CMDARG, cmd->arg);
mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
mci_writel(host, BMOD, bmod);
mci_writel(host, CTRL, temp);
mci_writel(host, BMOD, temp);
mci_writel(host, IDSTS64, IDMAC_INT_CLR);
mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
mci_writel(host, IDSTS, IDMAC_INT_CLR);
mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
mci_writel(host, DBADDR, host->sg_dma);
mci_writel(host, CTRL, temp);
mci_writel(host, BMOD, temp);
mci_writel(host, PLDMND, 1);
mci_writel(host, FIFOTH, fifoth_val);
mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
mci_writel(host, CDTHRCTL, 0);