arch/x86/kernel/cpu/mce/amd.c

894

mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0);

arch/x86/kernel/cpu/mce/amd.c

901

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1291

mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1713

mce_wrmsrq(MSR_IA32_MCG_STATUS, 0);

arch/x86/kernel/cpu/mce/core.c

772

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

927

mce_wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable);

arch/x86/kernel/cpu/mce/core.c

928

mce_wrmsrq(MSR_IA32_MCx_STATUS(1), 0);

arch/x86/kernel/cpu/mce/internal.h

328

noinstr void mce_wrmsrq(u32 msr, u64 v);