arch/x86/kernel/cpu/mce/amd.c

1180

err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));

arch/x86/kernel/cpu/mce/amd.c

554

addr = mca_msr_reg(bank, MCA_MISC);

arch/x86/kernel/cpu/mce/amd.c

901

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1291

mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1352

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/core.c

1896

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/core.c

1897

wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1899

rdmsrq(mca_msr_reg(i, MCA_CTL), msrval);

arch/x86/kernel/cpu/mce/core.c

2397

wrmsrq(mca_msr_reg(i, MCA_CTL), 0);

arch/x86/kernel/cpu/mce/core.c

2753

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/core.c

361

if (msr == mca_msr_reg(bank, MCA_STATUS))

arch/x86/kernel/cpu/mce/core.c

363

if (msr == mca_msr_reg(bank, MCA_ADDR))

arch/x86/kernel/cpu/mce/core.c

365

if (msr == mca_msr_reg(bank, MCA_MISC))

arch/x86/kernel/cpu/mce/core.c

664

m->misc = mce_rdmsrq(mca_msr_reg(i, MCA_MISC));

arch/x86/kernel/cpu/mce/core.c

670

m->addr = mce_rdmsrq(mca_msr_reg(i, MCA_ADDR));

arch/x86/kernel/cpu/mce/core.c

772

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

814

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/core.c

972

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/inject.c

752

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status);

arch/x86/kernel/cpu/mce/inject.c

753

rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status);

arch/x86/kernel/cpu/mce/inject.c

754

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0);