mc7
struct mc7 pmrx;
struct mc7 pmtx;
struct mc7 cm;
static inline unsigned int t3_mc7_size(const struct mc7 *p)
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
struct mc7 *mem;
struct mc7 *mem;
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
unsigned int size64 = mc7->size / 8; /* # of 64-bit words */
struct adapter *adap = mc7->adapter;
start *= (8 << mc7->width);
for (i = (1 << mc7->width) - 1; i >= 0; --i) {
t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
mc7->offset + A_MC7_BD_OP);
static void mc7_intr_handler(struct mc7 *mc7)
struct adapter *adapter = mc7->adapter;
u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
mc7->stats.corr_err++;
"data 0x%x 0x%x 0x%x\n", mc7->name,
t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
mc7->stats.uncorr_err++;
"data 0x%x 0x%x 0x%x\n", mc7->name,
t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
mc7->stats.parity_err++;
mc7->name, G_PE(cause));
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
mc7->offset + A_MC7_ERR_ADDR);
mc7->stats.addr_err++;
mc7->name, addr);
if (mc7->width == 0) {
t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
mc7->offset +
if (mc7->width > 1)
val >>= shift[mc7->width];
val64 |= (u64) val << (step[mc7->width] * i);
static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
struct adapter *adapter = mc7->adapter;
if (!mc7->size)
val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
mc7->name);
t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
t3_write_reg(adapter, mc7->offset + A_MC7_REF,
t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
(mc7->size << width) - 1);
t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
static void mc7_prep(struct adapter *adapter, struct mc7 *mc7,
mc7->adapter = adapter;
mc7->name = name;
mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;
cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);
mc7->width = G_WIDTH(cfg);