mlx4_cmd
mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
err = mlx4_cmd(dev, reg_id, 0, 0,
err = mlx4_cmd(dev, mailbox->dma,
err += mlx4_cmd(dev, mailbox->dma,
err = mlx4_cmd(dev, mailbox->dma,
err += mlx4_cmd(dev, mailbox->dma,
struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
return mlx4_cmd(dev, mailbox->dma, cq_num, opmod,
return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
err = mlx4_cmd(priv->mdev->dev, mailbox_in_dma, inmod,
err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
return mlx4_cmd(priv->mdev->dev, 0, 0, 0, MLX4_CMD_HW_HEALTH_CHECK,
err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
err = mlx4_cmd(dev, mailbox->dma, 0,
return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
err = mlx4_cmd(dev, 0, ((u32) err |
err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
err = mlx4_cmd(dev, mailbox->dma, port,
err = mlx4_cmd(dev, mailbox->dma, (vport << 8) | port,
return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX,
mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
err = mlx4_cmd(dev, in_param, 0, 0,
err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
err = mlx4_cmd(dev, regid, 0, 0,
return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
struct mlx4_cmd cmd;
err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
return mlx4_cmd(dev, mailbox->dma, mpt_index,
return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT,
err = mlx4_cmd(dev, in_param, RES_XRCD,
err = mlx4_cmd(dev, mailbox->dma,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
err = mlx4_cmd(dev, mailbox->dma, port,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
err = mlx4_cmd(dev, mailbox->dma, port, MLX4_SET_PORT_BEACON_OPCODE,
return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
ret = mlx4_cmd(dev, 0, qp->qpn, 2,
ret = mlx4_cmd(dev, mailbox->dma,
err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
err = mlx4_cmd(dev, inbox->dma,
mlx4_cmd(dev, vhcr->out_param, 0, 0,
mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
err = mlx4_cmd(dev, in_param,
err = mlx4_cmd(dev, in_param, srqn, 1,
err = mlx4_cmd(dev, in_param, cqn, 1,
err = mlx4_cmd(dev, in_param, mptn, 0,
mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
err = mlx4_cmd(dev, base, 0, 0,
err = mlx4_cmd(dev, slave, eqn & 0x3ff,
err = mlx4_cmd(dev, mailbox->dma,
if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
return mlx4_cmd(dev, mailbox->dma, srq_num, 0,
return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,