mipsxx_pmu_write_control
mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
mipsxx_pmu_write_control(idx,
mipsxx_pmu_write_control(3, 0);
mipsxx_pmu_write_control(3, 127<<5);
mipsxx_pmu_write_control(3, 191<<5);
mipsxx_pmu_write_control(3, 255<<5);
mipsxx_pmu_write_control(3, 319<<5);
mipsxx_pmu_write_control(3, 383<<5);
mipsxx_pmu_write_control(3, 575<<5);
mipsxx_pmu_write_control(2, 0);
mipsxx_pmu_write_control(2, 127<<5);
mipsxx_pmu_write_control(2, 191<<5);
mipsxx_pmu_write_control(2, 255<<5);
mipsxx_pmu_write_control(2, 319<<5);
mipsxx_pmu_write_control(2, 383<<5);
mipsxx_pmu_write_control(2, 575<<5);
mipsxx_pmu_write_control(1, 0);
mipsxx_pmu_write_control(1, 127<<5);
mipsxx_pmu_write_control(1, 191<<5);
mipsxx_pmu_write_control(1, 255<<5);
mipsxx_pmu_write_control(1, 319<<5);
mipsxx_pmu_write_control(1, 383<<5);
mipsxx_pmu_write_control(1, 575<<5);
mipsxx_pmu_write_control(0, 0);
mipsxx_pmu_write_control(0, 127<<5);
mipsxx_pmu_write_control(0, 191<<5);
mipsxx_pmu_write_control(0, 255<<5);
mipsxx_pmu_write_control(0, 319<<5);
mipsxx_pmu_write_control(0, 383<<5);
mipsxx_pmu_write_control(0, 575<<5);
mipsxx_pmu_write_control(3, 0);
mipsxx_pmu_write_control(2, 0);
mipsxx_pmu_write_control(1, 0);
mipsxx_pmu_write_control(0, 0);