mips_cm_revision
if (mips_cm_revision() >= CM_REV_CM3)
if (mips_cm_revision() < CM_REV_CM3_5)
if (mips_cm_revision() < CM_REV_CM3_5) {
if (mips_cm_revision() < CM_REV_CM3_5) {
mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
cm_rev = mips_cm_revision();
if (mips_cm_revision() < CM_REV_CM3) {
revision = mips_cm_revision();
if (mips_cm_revision() >= CM_REV_CM3)
if (mips_cm_revision() >= CM_REV_CM3)
if (mips_cm_revision() < CM_REV_CM3) {
uasm_i_addiu(&p, GPR_T0, GPR_ZERO, mips_cm_revision() < CM_REV_CM3
if (mips_cm_revision() >= CM_REV_CM3_5)
if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
if (mips_cm_revision() < CM_REV_CM3)
if (mips_cm_revision() >= CM_REV_CM3) {
if (mips_cm_revision() >= CM_REV_CM3_5) {
if (mips_cm_revision() >= CM_REV_CM3) {
if (mips_cm_revision() >= CM_REV_CM3) {
if (mips_cm_revision() >= CM_REV_CM3)
if (mips_cm_revision() < CM_REV_CM2_5)
if (mips_cm_revision() < CM_REV_CM2_5)
if (mips_cm_revision() < CM_REV_CM2_5)
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
if ((mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) &&