CLK_SCLK_UART0
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",