mii_write
void (*mii_write)(struct net_device *dev,
mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
mii_write (dev, phy_addr, MII_ADVERTISE, anar);
mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_ADVERTISE, 0);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_ADVERTISE, anar);
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mii_write (dev, phy_addr, MII_ADVERTISE, 0);
mii_write(dev, np->phy_addr, 31, 0x0001);
mii_write(dev, np->phy_addr, 27, 0x01e0);
mii_write(dev, np->phy_addr, 31, 0x0002);
mii_write(dev, np->phy_addr, 27, 0xeb8e);
mii_write(dev, np->phy_addr, 31, 0x0000);
mii_write(dev, np->phy_addr, 30, 0x005e);
mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
err = mii_write(np, np->phy_addr,
err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);