arch/powerpc/boot/4xx.c

106

banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));

arch/powerpc/boot/4xx.c

109

banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));

arch/powerpc/boot/4xx.c

112

banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));

arch/powerpc/boot/4xx.c

115

banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));

arch/powerpc/boot/4xx.c

284

while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)

arch/powerpc/boot/4xx.c

300

bxcr = mfdcr(DCRN_EBC0_CFGDATA);

arch/powerpc/boot/4xx.c

320

u32 sys0 = mfdcr(DCRN_CPC0_SYS0);

arch/powerpc/boot/4xx.c

321

u32 cr0 = mfdcr(DCRN_CPC0_CR0);

arch/powerpc/boot/dcr.h

172

mfdcr(DCRN_SDR0_CONFIG_DATA); })

arch/powerpc/boot/dcr.h

190

mfdcr(DCRN_CPR0_CFGDATA); })

arch/powerpc/boot/dcr.h

30

mfdcr(DCRN_SDRAM0_CFGDATA); })

arch/powerpc/include/asm/dcr-native.h

29

#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)

arch/powerpc/platforms/44x/fsp2.c

100

pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0));

arch/powerpc/platforms/44x/fsp2.c

101

pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1));

arch/powerpc/platforms/44x/fsp2.c

102

pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH));

arch/powerpc/platforms/44x/fsp2.c

103

pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL));

arch/powerpc/platforms/44x/fsp2.c

106

pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH));

arch/powerpc/platforms/44x/fsp2.c

107

pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL));

arch/powerpc/platforms/44x/fsp2.c

108

pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));

arch/powerpc/platforms/44x/fsp2.c

109

pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));

arch/powerpc/platforms/44x/fsp2.c

110

pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH));

arch/powerpc/platforms/44x/fsp2.c

111

pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL));

arch/powerpc/platforms/44x/fsp2.c

112

pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));

arch/powerpc/platforms/44x/fsp2.c

113

pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));

arch/powerpc/platforms/44x/fsp2.c

121

pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR));

arch/powerpc/platforms/44x/fsp2.c

122

pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR));

arch/powerpc/platforms/44x/fsp2.c

123

pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR));

arch/powerpc/platforms/44x/fsp2.c

126

pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR));

arch/powerpc/platforms/44x/fsp2.c

127

pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR));

arch/powerpc/platforms/44x/fsp2.c

139

pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC));

arch/powerpc/platforms/44x/fsp2.c

140

pr_err("RPERR0: 0x%08x\n", mfdcr(DCRN_CONF_RPERR0));

arch/powerpc/platforms/44x/fsp2.c

141

pr_err("RPERR1: 0x%08x\n", mfdcr(DCRN_CONF_RPERR1));

arch/powerpc/platforms/44x/fsp2.c

152

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT));

arch/powerpc/platforms/44x/fsp2.c

154

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1));

arch/powerpc/platforms/44x/fsp2.c

156

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2));

arch/powerpc/platforms/44x/fsp2.c

158

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT));

arch/powerpc/platforms/44x/fsp2.c

160

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0));

arch/powerpc/platforms/44x/fsp2.c

162

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1));

arch/powerpc/platforms/44x/fsp2.c

164

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2));

arch/powerpc/platforms/44x/fsp2.c

166

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3));

arch/powerpc/platforms/44x/fsp2.c

168

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL));

arch/powerpc/platforms/44x/fsp2.c

170

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0));

arch/powerpc/platforms/44x/fsp2.c

172

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0));

arch/powerpc/platforms/44x/fsp2.c

174

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0));

arch/powerpc/platforms/44x/fsp2.c

176

mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0));

arch/powerpc/platforms/44x/fsp2.c

178

mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0));

arch/powerpc/platforms/44x/fsp2.c

180

mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1));

arch/powerpc/platforms/44x/fsp2.c

182

mfdcr(DCRN_PLB6MCIF_BESR0));

arch/powerpc/platforms/44x/fsp2.c

184

mfdcr(DCRN_PLB6MCIF_BEARL));

arch/powerpc/platforms/44x/fsp2.c

186

mfdcr(DCRN_PLB6MCIF_BEARH));

arch/powerpc/platforms/44x/fsp2.c

248

val = mfdcr(DCRN_PLB6_CR0);

arch/powerpc/platforms/44x/fsp2.c

72

pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0));

arch/powerpc/platforms/44x/fsp2.c

73

pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1));

arch/powerpc/platforms/44x/fsp2.c

74

pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2));

arch/powerpc/platforms/44x/fsp2.c

75

pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU));

arch/powerpc/platforms/44x/fsp2.c

76

pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR));

arch/powerpc/platforms/44x/fsp2.c

86

pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD));

arch/powerpc/platforms/44x/fsp2.c

87

pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR));

arch/powerpc/platforms/44x/fsp2.c

90

pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR));

arch/powerpc/platforms/44x/fsp2.c

91

pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH));

arch/powerpc/platforms/44x/fsp2.c

92

pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL));

arch/powerpc/platforms/44x/fsp2.c

95

pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR));

arch/powerpc/platforms/44x/fsp2.c

96

pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH));

arch/powerpc/platforms/44x/fsp2.c

97

pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL));

arch/powerpc/platforms/44x/fsp2.h

256

data = mfdcr(DCRN_CMU_DATA); \

arch/powerpc/platforms/44x/fsp2.h

268

data = mfdcr(DCRN_L2CDCRDI); \

arch/powerpc/platforms/44x/soc.c

127

mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);

arch/powerpc/platforms/44x/soc.c

129

mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);

arch/powerpc/platforms/44x/soc.c

131

mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);

arch/powerpc/platforms/44x/soc.c

133

mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);

arch/powerpc/platforms/44x/soc.c

135

mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);

arch/powerpc/platforms/44x/soc.c

138

r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &

arch/powerpc/platforms/44x/soc.c

147

while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))

arch/powerpc/platforms/44x/soc.c

154

r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &

arch/powerpc/platforms/44x/soc.c

159

r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &

arch/powerpc/platforms/44x/soc.c

167

r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);

arch/powerpc/platforms/44x/soc.c

37

while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))

arch/powerpc/platforms/44x/soc.c

40

return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);

arch/powerpc/platforms/44x/soc.c

45

u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);

arch/powerpc/platforms/44x/uic.c

104

er = mfdcr(uic->dcrbase + UIC_ER);

arch/powerpc/platforms/44x/uic.c

152

tr = mfdcr(uic->dcrbase + UIC_TR);

arch/powerpc/platforms/44x/uic.c

153

pr = mfdcr(uic->dcrbase + UIC_PR);

arch/powerpc/platforms/44x/uic.c

211

msr = mfdcr(uic->dcrbase + UIC_MSR);

arch/powerpc/platforms/44x/uic.c

328

msr = mfdcr(primary_uic->dcrbase + UIC_MSR);

arch/powerpc/platforms/44x/uic.c

64

er = mfdcr(uic->dcrbase + UIC_ER);

arch/powerpc/platforms/44x/uic.c

78

er = mfdcr(uic->dcrbase + UIC_ER);