mfc_write
mfc_write(dev, args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
mfc_write(dev, args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
mfc_write(dev, args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
mfc_write(dev, args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD);
mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6);
mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */
mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6);
mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6);
mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6);
mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
mfc_write(dev, dev->dma_base[BANK_L_CTX],
mfc_write(dev, dev->dma_base[BANK_L_CTX],
mfc_write(dev, dev->dma_base[BANK_R_CTX],
mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
mfc_write(dev, p->rc_framerate_num * 1000
mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL);
mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL);
mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) <<
mfc_write(dev,
mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF);
mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) <<
mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) <<
mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC &
mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) |
mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);
mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);
mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
mfc_write(dev, ctx->total_dpb_count | dpb,
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR);
mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma),
mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK)
mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR);
mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE);
mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR);
mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR);
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETA(buf_addr1),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETB(buf_addr2),
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR);
mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR);
mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX);
mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX);
mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON);
mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL);
mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB);
mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT);
mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB);
mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT);
mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL);
mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
mfc_write(dev, p->rc_bitrate,
mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE);
mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA);
mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT);
mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL);
mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF);
mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF);
mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE);
mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE);
mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF);
mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
mfc_write(dev, p->rc_framerate_num * 1000
mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL);
mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL);
mfc_write(dev, framerate,
mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);