mfc_read
cur_cmd = mfc_read(dev, S5P_FIMV_HOST2RISC_CMD);
status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));
reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | (
dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT;
return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT;
return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS);
return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS);
return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) &
return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES);
reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) &
return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2);
return mfc_read(dev, S5P_FIMV_SI_HRESOL);
return mfc_read(dev, S5P_FIMV_SI_VRESOL);
return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER);
return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1);
return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE);
return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE);
dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
(mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) << MFC_OFFSET_SHIFT);
(mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) << MFC_OFFSET_SHIFT);
reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL);
reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);