meta_info
struct drm_amdgpu_info_uq_metadata meta_info = {};
ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx);
ret = copy_to_user(out, &meta_info,
min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0;
ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute);
ret = copy_to_user(out, &meta_info,
min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0;
ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma);
ret = copy_to_user(out, &meta_info,
min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0;
fw_meta_info = &adev->dm.dmub_srv->meta_info;
if (!dc_dmub_srv->dmub->meta_info.feature_bits.bits.cursor_offload_v1_support)
dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) {
struct dmub_fw_meta_info meta_info;
memcpy(&dmub->meta_info, params->fw_info, sizeof(*params->fw_info));
u32 meta_info, vlan_info;
meta_info = get_unaligned_be32(data);
while (meta_info) {
switch (meta_info & NFP_NET_META_FIELD_MASK) {
meta_info >>= NFP_NET_META_FIELD_SIZE;
meta_info & NFP_NET_META_FIELD_MASK,
meta_info >>= NFP_NET_META_FIELD_SIZE;
u32 meta_info, vlan_info;
meta_info = get_unaligned_be32(data);
while (meta_info) {
switch (meta_info & NFP_NET_META_FIELD_MASK) {
meta_info >>= NFP_NET_META_FIELD_SIZE;
meta_info & NFP_NET_META_FIELD_MASK,
meta_info >>= NFP_NET_META_FIELD_SIZE;
desc->meta_info = FIELD_PREP(HAL_CE_SRC_DESC_META_INFO_DATA, id);
u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
desc->meta_info = le32_encode_bits(id, HAL_CE_SRC_DESC_META_INFO_DATA);
__le32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
__le32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
struct meta_info *meta;
struct meta_info *meta = data_meta;