drivers/gpu/drm/meson/meson_osd_afbcd.c

282

meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB |

drivers/gpu/drm/meson/meson_osd_afbcd.c

285

meson_rdma_writel_sync(priv, 0, VIU_SW_RESET);

drivers/gpu/drm/meson/meson_osd_afbcd.c

315

meson_rdma_writel_sync(priv, VPU_MAFBC_IRQ_SURFACES_COMPLETED |

drivers/gpu/drm/meson/meson_osd_afbcd.c

321

meson_rdma_writel_sync(priv, VPU_MAFBC_S0_ENABLE,

drivers/gpu/drm/meson/meson_osd_afbcd.c

324

meson_rdma_writel_sync(priv, VPU_MAFBC_DIRECT_SWAP,

drivers/gpu/drm/meson/meson_osd_afbcd.c

359

meson_rdma_writel_sync(priv, format,

drivers/gpu/drm/meson/meson_osd_afbcd.c

362

meson_rdma_writel_sync(priv, priv->viu.osd1_addr,

drivers/gpu/drm/meson/meson_osd_afbcd.c

364

meson_rdma_writel_sync(priv, 0,

drivers/gpu/drm/meson/meson_osd_afbcd.c

367

meson_rdma_writel_sync(priv, priv->viu.osd1_width,

drivers/gpu/drm/meson/meson_osd_afbcd.c

369

meson_rdma_writel_sync(priv, ALIGN(priv->viu.osd1_height, 32),

drivers/gpu/drm/meson/meson_osd_afbcd.c

372

meson_rdma_writel_sync(priv, 0,

drivers/gpu/drm/meson/meson_osd_afbcd.c

374

meson_rdma_writel_sync(priv, priv->viu.osd1_width - 1,

drivers/gpu/drm/meson/meson_osd_afbcd.c

376

meson_rdma_writel_sync(priv, 0,

drivers/gpu/drm/meson/meson_osd_afbcd.c

378

meson_rdma_writel_sync(priv, priv->viu.osd1_height - 1,

drivers/gpu/drm/meson/meson_osd_afbcd.c

381

meson_rdma_writel_sync(priv, MESON_G12A_AFBCD_OUT_ADDR,

drivers/gpu/drm/meson/meson_osd_afbcd.c

383

meson_rdma_writel_sync(priv, 0,

drivers/gpu/drm/meson/meson_osd_afbcd.c

386

meson_rdma_writel_sync(priv, priv->viu.osd1_width *

drivers/gpu/drm/meson/meson_rdma.h

18

void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg);