Symbol: meson_parm_read
drivers/clk/meson/clk-cpu-dyndiv.c
26
meson_parm_read(clk->map, &data->div),
drivers/clk/meson/clk-dualdiv.c
54
setting.dual = meson_parm_read(clk->map, &dualdiv->dual);
drivers/clk/meson/clk-dualdiv.c
55
setting.n1 = meson_parm_read(clk->map, &dualdiv->n1) + 1;
drivers/clk/meson/clk-dualdiv.c
56
setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1;
drivers/clk/meson/clk-dualdiv.c
57
setting.n2 = meson_parm_read(clk->map, &dualdiv->n2) + 1;
drivers/clk/meson/clk-dualdiv.c
58
setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1;
drivers/clk/meson/clk-mpll.c
83
sdm = meson_parm_read(clk->map, &mpll->sdm);
drivers/clk/meson/clk-mpll.c
84
n2 = meson_parm_read(clk->map, &mpll->n2);
drivers/clk/meson/clk-phase.c
108
val = meson_parm_read(clk->map, &tph->ph0);
drivers/clk/meson/clk-phase.c
158
val = meson_parm_read(clk->map, &tph->ph);
drivers/clk/meson/clk-phase.c
170
val = meson_parm_read(clk->map, &tph->ph);
drivers/clk/meson/clk-phase.c
43
val = meson_parm_read(clk->map, &phase->ph);
drivers/clk/meson/clk-phase.c
94
val = meson_parm_read(clk->map, &tph->ph0);
drivers/clk/meson/clk-pll.c
285
if (meson_parm_read(clk->map, &pll->l))
drivers/clk/meson/clk-pll.c
300
meson_parm_read(clk->map, &pll->rst))
drivers/clk/meson/clk-pll.c
303
if (!meson_parm_read(clk->map, &pll->en) ||
drivers/clk/meson/clk-pll.c
304
!meson_parm_read(clk->map, &pll->l))
drivers/clk/meson/clk-pll.c
436
enabled = meson_parm_read(clk->map, &pll->en);
drivers/clk/meson/clk-pll.c
79
n = meson_parm_read(clk->map, &pll->n);
drivers/clk/meson/clk-pll.c
89
m = meson_parm_read(clk->map, &pll->m);
drivers/clk/meson/clk-pll.c
92
meson_parm_read(clk->map, &pll->frac) :
drivers/clk/meson/sclk-div.c
152
hi = meson_parm_read(clk->map, &sclk->hi);
drivers/clk/meson/sclk-div.c
214
if (meson_parm_read(clk->map, &sclk->div))
drivers/clk/meson/sclk-div.c
231
val = meson_parm_read(clk->map, &sclk->div);
drivers/clk/meson/vclk.c
127
return meson_parm_read(clk->map, &vclk->enable);
drivers/clk/meson/vclk.c
44
return meson_parm_read(clk->map, &vclk->enable);
drivers/clk/meson/vclk.c
69
return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
drivers/clk/meson/vid-pll-div.c
82
div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
drivers/clk/meson/vid-pll-div.c
83
meson_parm_read(clk->map, &pll_div->sel));